Field programmable gate arrays (FPGAs) are known to those skilled in the art to include arrays of uncommitted, programmable logic cells having both combinational and synchronous logic circuits therein. Typically, the logic cells are programmably interconnected by a programmable interconnect network. A complex user-defined logic function can thus be performed by an FPGA by appropriately programming and interconnecting the logic cells.
Advanced FPGAs may also include programmable input/output (I/O) resources for transferring data to and from the array of logic cells. The I/O resources may be programmable to control the direction of signal propagation therethrough (i.e. either input or output), and may additionally be programmed per several additional selectively activated control configurations (e.g., impedance, slew rate, pull-ups, polarity, etc.). FPGAs often employ many I/O terminals, each of which may be individually configured per its associated programmable I/O resources. Programmable clock networks may also be employed in an FPGA to distribute one or a plurality of clock signals to various sequential circuits of the array. Each of the above FPGA subsystems is normally considered part of a "functional" portion of an FPGA. These subsystems are referred to hereinafter singly or collectively, as "programmable resources." Exemplary programmable resources are disclosed in the above identified co-pending U.S. Patent Applications.
A variety of programming technologies are currently available for FPGAs. For example, non-volatile fuse or anti-fuse links can be employed in the array to provide selective connection between array resources. To program these lines, each terminal of each two-terminal link must be independently addressable for enabling selective placement of appropriate programming voltages across the link. Thus, additional configuration support circuitry is necessary to provide the requisite addressing and routing of the programming voltages for configuring the array. Floating-gate EPROM/EEPROM transistors can also be used to provide array programmability, and would be similarly placed in the array and independently addressed for applying programming voltages thereto.
Static RAM (SRAM) technologies are also available for controlling the programmable resources of a FPGA. A simple programmable resource of the FPGA includes a CMOS pass gate. The pass gate is controlled by an underlying SRAM cell which holds a predetermined programmed state. This programmed state, i.e. configuration data bit as stored in the SRAM cell, determines whether the pass gate conducts. A homogeneous array of SRAM cells can thus be provided as a relatively independent subsystem in an FPGA for establishing the configurations of the associated programmable resources of the FPGA. Access to the array of SRAM cells is provided using standard access techniques controlled by a configuration logic subsystem of the FPGA.
It is thus apparent that, in addition to the programmable resources of a programmable gate array, additional configuration subsystems are necessary for enabling programming of the array. In the above SRAM FPGA example, a homogeneous array of SRAM cells is provided for configuring associated programmable resources of the FPGA, along with associated configuration logic for controlling access thereto. From the standpoint of semiconductor design and fabrication, the provision of multiple, heterogeneous subsystems in a single semiconductor package leads to serious concerns regarding circuit testability, including fault detection and isolation. It would thus be advantageous to provide a comprehensive test strategy for enabling testing of the configuration subsystems and programmable resources of an FPGA. This test strategy itself may include the provision of additional test subsystems within the FPGA, which test subsystems should also be testable. Thus, the test strategies, to the extent possible, must encompass all of the resources and subsystems of the FPGA, including the test subsystems.
The programmable resources, and the configuration and test subsystems, though different in their respective circuitry and functions, are nevertheless highly interdependent. This interdependence significantly complicates the test strategies employed. For example, it is often desirous to test the combinational logic of the logic cells, which logic cells are programmed into a given state by the configuration subsystem. The integrity of the logic cell tests, however, may be adversely influenced by errors in the configuration subsystems, and by errors in the test subsystems. Thus, it is desirous to employ a test strategy which considers, to the extent possible, the interdependence between the various resources and subsystems in an FPGA.
Known boundary scan techniques involve the provision of dual latch sets, e.g. LSSD registers, at the perimeter of a chip, in association with the I/O terminals thereof. The latch sets are interconnected as a shift register scan chain. Test stimuli can be loaded serially into the scan chain and applied to an internal circuit of the chip. The scan chain can likewise capture result data as provided by the internal circuit in response to the test stimuli. These results can then be shifted out of the shift register and compared to expected results. Scan-in, scan-out, and several clock terminals of the chip are provided for enabling operation of the scan chain. Accordingly, faults can be detected in the internal circuit of the chip without requiring external test interfacing to each I/O terminal of the chip. However, with increasing circuit densities, and especially considering the heterogeneous nature of the circuits in an FPGA, fault detection may be possible with boundary scan techniques, but fault isolation may be difficult. It is thus desirous to employ test subsystems which provide a greater degree of fault isolation during testing of the various resources and subsystems in an FPGA.
Level-sensitive scan design (LSSD) test techniques are also known and involve segmenting a logic circuit into combinational and synchronous logic circuitry. The synchronous circuits are connected into a serial shift register scan chain which bound or segment regions of the logic circuitry. Like the boundary scan techniques, test stimuli are shifted into the shift register scan chain and applied to the logic circuit. Result data is captured into the scan chain as effected by the associated logic circuitry or segment thereof. The captured result data is then shifted out for analysis. Again, reduced pin count testing is achieved in that external test equipment need only access the scan-in, scan-out and appropriate clock pins.
In typical FPGAs, it is somewhat difficult to clearly segment all of the combinational circuits by converting the synchronous circuits thereof into serial shift registers. For example, if each of the synchronous circuits in each logic cell is converted and connected within an associated serial shift register scan chain, the intervening programmable interconnect network would not be clearly segmented and would likely contain untestable regions. This problem is especially severe if the interconnect network is large and complex. Thus, it is desirous to provide a test strategy which provides adequate testing of the heterogeneous combinational and synchronous resources of an FPGA, enables ready segmentation thereof and overcomes the weakness of using a pure LSSD approach.
The provision of a high performance test strategy, as discussed above, may require at least some additional test subsystems in the array. However, like the known shift register techniques, it is desirous to minimize, to the extent possible, the number of I/O terminals necessary to operate the test subsystems. Additionally, it is desirous to support testing of multiple FPGA chips in a system with a minimum amount of signal interface circuitry and external test equipment.